A trench type and a stacked type have generally been known as a basic structure of a DRAM. The trench type is one wherein each of capacitative elements (hereinafter called simply "capacitors") for information storage is formed inside a trench defined in a substrate. The stacked type is one wherein each of capacitors is formed over its corresponding transfer transistor (hereinafter called selection MISFET (Metal Insulator Semiconductor Field Effect Transistor)) on the surface of a substrate. The stacked type is further classified into a CUB (Capacitor Under Bit-line) type wherein each capacitor is placed below its corresponding bit line and a COB (Capacitor Over Bit-line) type wherein each capacitor is located over the bit line. 64M-bit and later products which have gone into mass production, are of stacked types excellent in characteristic of a reduction in each cell area. The COB type is becoming mainstream.
A structure of a DRAM having each COB type memory cell is illustrated by way of example as follows. Namely, The memory cells of the DRAM having the COB type memory cells are placed at points where a plurality of word lines and a plurality of bit lines placed on a main surface of a semiconductor substrate in matrix form intersect respectively. Each memory cell comprises one selection MISFET and one capacitor electrically connected to the selection MISFET. The selection MISFET is formed in an active region whose periphery is surrounded by device isolation regions, and is comprised principally of a gate oxide film, a gate electrode formed integrally with each word line, and a pair of semiconductor regions each constituting a source and drain. Each of the bit lines is placed over its corresponding selection MISFET and electrically connected to one of the source and drain shared between two selection MISFETs adjacent in its extending direction. Similarly, each capacitor is placed over its corresponding selection MISFET and electrically connected to the other of the source and drain. In order to supplement a reduction in the amount (Cs) of an electrical charge stored in each capacitor due to scaling down of each memory cell, a lower electrode (storage electrode) of the capacitor placed over the bit line is processed in cylindrical form to increase a surface area thereof, and a capacitive insulating film and an upper electrode (plate electrode) are formed thereover.
In such a structure of COB type memory cell, the bit lines and the source and drain regions of the selection MISFET are electrically connected to one another by plugs each composed of a polycrystalline silicon film or the like. Since plugs for capacitor connection are also formed simultaneously with plugs for bit line connection in general, at least an insulating film corresponding to one layer is formed between the plug and bit line to isolate the bit line and the plug for capacitor connection from each other. Thus, the bit lines and the plugs are connected to one another through bit line connecting holes respectively. There is a demand for a reduction in the capacitance of each bit line in terms of an improvement in the operating speed of a DRAM and an improvement in the sensitivity for the detection of each stored charge. There is further a demand for scaling down or miniaturization of members such as the bit lines even in terms of the implementation of scaling down. In order to meet these demands, a technique is known wherein the bit lines are formed by a damascene method and side wall spacers each composed of a silicon nitride film are formed over inner side walls as described in the international publication WO98/28795, for example. Owing to such a technique, the bit lines are made thin and the distance between the bit lines is made long to reduce the capacitance between the bit lines, whereby the speeding up of the DRAM and the sensitivity for the detection of each stored capacitance are improved.